Computer Organization and Architecture
Storage and I/O Systems
Module VIII: Storage and I/O Systems. This module explores the design and management of Input/Output (I/O) systems, focusing on how a processor coordinates data movement with diverse external peripheral devices. Learners will analyze data transfer mechanisms, compare standard bus interconnections (Processor-Memory, I/O, and Backplane buses), examine the operational control flags of Direct Memory Access (DMA) controllers, and study dedicated I/O processors and interface registers.
1. General I/O System Architecture and Control
An Input/Output (I/O) system connects the central processor and main memory to external peripherals like storage disks, displays, network interfaces, keyboards, and mice. Because these devices vary by many orders of magnitude in speed, data format, and control logic, a standardized interface architecture is required.
Data Transfer Control Primitives
Peripheral devices are connected to the system via specialized I/O Controllers or device adapters containing interface ports or registers. Handling an I/O operation involves two components:
1. Control / Command Signaling
The processor issues task commands (e.g., read, write, seek) or continuously checks peripheral status flags to see if a device is idle, busy, or experiencing an execution error.
2. Data Transfer Pathways
The actual mechanism used to route blocks of binary data bytes between main memory and the internal buffers of the hardware peripheral.
2. Bus Interconnections and Taxonomy
To link the CPU, memory subsystems, and I/O interfaces together, computer architectures deploy electronic communication channels called Buses.
Processor-Memory Bus
- Design Traits: Very short physical length, featuring minimal connection taps to keep circuit noise negligible.
- Performance: Exceptionally fast with maximized data bandwidth. Highly optimized for synchronous, high-frequency transfers directly between the CPU core and the RAM cache controller.
- Limitation: System-specific; not built to plug standard, generic third-party peripherals directly into its lines.
Input/Output (I/O) Bus
- Design Traits: Physically longer line layout with high tap capacities to support many different expanding adapters. Conforms to industry standards (e.g., PCIe, USB, SATA).
- Performance: Slower clock frequencies and lower data bandwidth than a processor-memory bus.
- Interconnect: Connected to the high-speed Processor-Memory bus using a specialized bridging module called a Bus Adapter.
Backplane Bus
- Design Traits: A unified, single communication plane where the CPU, memory modules, and all peripheral hardware ports link up along the exact same backplane wiring system.
- Trade-off: Industry-standard and cheap to manufacture (avoids expensive bridge adapters). Forced to share slow I/O actions with memory lines, compromising core performance.
3. Data Transfer Coordination Mechanisms
Architectures manage data movement between peripheral controller interfaces and main memory using three primary communication protocols:
Protocol: The CPU repeatedly checks a device's status register in a tight loop until the hardware sets its Done flag to indicate readiness.
Evaluation: Straightforward to code, but introduces severe CPU processing waste by stalling its entire executing thread waiting on slow mechanical actions.
Protocol: CPU issues command and resumes other tasks. When the peripheral finishes, it issues an Interrupt Request (IRQ) over the control bus.
Evaluation: Saves cycle waste. However, interrupting the processor for every single byte during high-speed transfers creates an overwhelming context-switching bottleneck.
Protocol: For bulk data operations, a specialized hardware component (DMA Controller) takes temporary control of the system bus.
Evaluation: Streams large data blocks directly between main memory and the I/O interface entirely in the background, bypassing the CPU processor entirely.
4. Direct Memory Access (DMA) Controllers
A standard DMA interface controller exposes a set of addressable control registers to the system bus. The processor sets up a transfer by writing values into these registers before relinquishing control of the bus:
| Core Interface Registers | Purpose during Setup |
|---|---|
| Starting Address Register | Stores the initial 32-bit physical main memory pointer location where the data block read or write sequence will begin. |
| Word Count Register | Holds the integer count indicating the total number of bytes or words that must be transferred across the bus during this continuous operation. |
| Status and Control Register |
|
5. Advanced Architectures: I/O Processors
As systems scale up, a simple DMA controller can still place coordination overhead on the main processor. To completely decouple I/O bottlenecks from computational threads, advanced systems employ an I/O Processor (also known as a Channel Controller).
The I/O Processing Model
An I/O Processor is a small, dedicated microprocessing execution block built directly into the I/O subsystem. It possesses a specialized RISC instruction vocabulary optimized exclusively for data routing operations.
(Issues Channel Command)
I/O Channel Processor
- Executes channel program
- Fetches blocks directly from disk
- Checks error codes
- Writes directly to RAM
Operational Workflow
Rather than tracking individual buffer locations, the main CPU creates an independent program in system memory called a Channel Program outlining transport and error checking.
The main CPU writes the starting address of this program into the I/O Processor's Interface Registers and executes a channel instruction.
The I/O Processor independently executes the code, fetches streams, handles priorities, and alerts the main CPU via a single interrupt only once the entire complex automation task is complete.