Computer Organization and Architecture

MIPS - Language of the Computer

Module III: MIPS - Language of the Computer. This module introduces the Instruction Set Architecture (ISA) and the MIPS programming model: registers, instruction formats (R/I/J), addressing modes, and how high-level control flow maps to machine instructions.

1. Instruction Set Architecture & Stored Program

The ISA is the contract between software and hardware - the set of operations, register file visibility, data types, and addressing modes that software relies upon. The Stored Program Concept stores both instructions and data in the same memory space, enabling the control unit to fetch and execute instruction sequences dynamically.

2. MIPS Register Architecture & Conventions

MIPS uses a 32-register file (32-bit words). The table below summarizes conventional usage names and hardware intent.

Register	Name	Purpose
$0	$zero	Hardwired zero (reads 0, writes ignored)
$1	$at	Assembler temporary (pseudo-instructions)
$2-$3	$v0-$v1	Return values
$4-$7	$a0-$a3	Argument registers
$8-$15	$t0-$t7	Temporaries (not preserved across calls)
$16-$23	$s0-$s7	Saved temporaries (callee must restore)
$24-$25	$t8-$t9	More temporaries
$26-$27	$k0-$k1	Kernel (reserved for OS traps)
$28	$gp	Global pointer for static data
$29	$sp	Stack pointer
$30	$fp	Frame pointer
$31	$ra	Return address for subroutines

3. Operands, Memory Mapping & Alignment

MIPS is byte-addressable, but many instructions operate on 32-bit words (4 bytes). Word addresses must be multiples of 4 - this is the alignment restriction.

Load / Compute / Store sequence

# Pseudocode sequence
lw $t0, 0($s0)   # load from memory into register
add $t1, $t0, $t2
sw $t1, 4($s0)   # write back

4. MIPS Instruction Formats (R / I / J)

All MIPS instructions are 32 bits wide. The three common formats are:

R-Type (Register)

op | rs | rt | rd | shamt | funct 31-26 25-21 20-16 15-11 10-6 5-0

I-Type (Immediate / Loads)

op | rs | rt | immediate 31-26 25-21 20-16 15-0

J-Type (Jump)

op | target 31-26 25-0

5. Software Control Flow - Branches, Loops, Subroutines

Common control-flow instructions map high-level constructs to machine steps:

Loop:  bne $s1, $s2, Exit add $s3, $s3, $s4 addi $s1, $s1, 1 j Loop Exit:

Subroutines use jal and jr $ra to call and return.

6. MIPS Addressing Modes - Quick Reference

Register: operands are in registers (e.g., add $s1, $s2, $s3).
Immediate: small constants encoded in instruction (e.g., addi $s1, $s2, 100).
Base/Displacement: memory address = base register + offset (e.g., lw $s1, 24($s2)).
PC-relative: branch target computed from PC + offset (used by beq/bne).
Pseudo-direct: used by jumps; the 26-bit target is combined with high PC bits.

Performance Analysis Computer Arithmetic