Computer Organization and Architecture

Computer Arithmetic

Module IV: Computer Arithmetic. This module explores how numbers are structurally represented and mathematically manipulated at the hardware level. It covers two's complement signed integers, sign extension, overflow detection, multiplication/division hardware, and IEEE 754 floating-point representation.

1. Number Representation & Two's Complement

Modern processors use fixed bit-width systems (e.g., 32-bit MIPS words) to manipulate numbers.

Unsigned Integers

All 32 bits map directly to binary magnitude positions:

Value = ∑(d_i × 2ⁱ), i=0 to 31

Range: 0 to 4,294,967,295 (2³² - 1)

Signed Integers (Two's Complement)

To handle negative numbers efficiently, the most significant bit (bit 31, the Sign Bit) acts as a negative weight:

Value = −d₃₁ × 2³¹ + ∑(d_i × 2ⁱ), i=0 to 30

Bit 31 = 0: Positive number or zero
Bit 31 = 1: Negative number

Minimum Value

−2,147,483,648 (−2³¹)

Maximum Value

+2,147,483,647 (+2³¹ − 1)

2. Sign Extension & Overflow Detection

Sign Extension Hardware

When moving data between registers of different capacities (e.g., 16-bit immediate to 32-bit register), the hardware must preserve the numeric value:

Positive Numbers: Upper bits filled with 0
Negative Numbers: Upper bits filled with 1

The sign bit is replicated across all newly created higher-order bit positions.

Arithmetic Overflow Detection

An Overflow Exception occurs when an arithmetic result falls outside the representable range.

Key Rules:

Overflow can only occur when adding two positive or two negative values
Adding opposite signs never produces overflow
Detection: if result sign conflicts with operand signs → overflow

Operand 1	Operand 2	Operation	Result Sign	Overflow?
Positive	Positive	Add	Negative	YES
Negative	Negative	Add	Positive	YES
Positive	Negative	Subtract	Negative	YES
Negative	Positive	Subtract	Positive	YES

3. Multiplication & Division Hardware

Sequential Multiplication

Multiplying two 32-bit integers produces a result up to 64 bits wide.

Multiplier Bit = 1  =>  Shift Multiplicand Left, then Add to Product Multiplier Bit = 0  =>  Shift Multiplicand Left, no Addition

Hardware Iteration (32 cycles):

Evaluate LSB of Multiplier register
- If 1: Add Multiplicand to Product
- If 0: Skip addition
Shift Multiplicand register left by 1 bit
Shift Multiplier register right by 1 bit

The hardware integrates a 64-bit multiplicand register, 64-bit ALU adder, 64-bit product register, and 32-bit multiplier register with control logic orchestrating the shifts and additions.

4. Floating-Point Representation (IEEE 754)

Real numbers, fractions, and scientific notation cannot use fixed-position integer schemes. The IEEE 754 Floating-Point Standard encodes real numbers using normalized scientific notation.

Normalized Scientific Form

Every floating-point number is standardized as:

± 1.fraction × 2^exponent

Single Precision (32-bit) Format

The 32 bits are divided into three component fields:

[ S ] [ Biased Exponent ] [ Significand Fraction ]

31 30-23 22-0

Sign Bit (1 bit)

Bit 31: 0 = positive, 1 = negative

Biased Exponent (8 bits)

Bits 30-23: Real exponent + 127 (allows negative powers)

Significand Fraction (23 bits)

Bits 22-0: Fractional part; leading '1.' is assumed

Evaluation Formula

Value = (−1)^S × (1 + Fraction) × 2^{(Biased Exponent − 127)}

Floating-Point Addition Steps

Align Binary Decimal Points - Shift smaller exponent significand right
Add Significand Fractions - Perform addition on aligned operands
Normalize the Result - Adjust decimal point and update exponent
Perform Rounding - Apply rounding rules to fit back into 32-bit format

Unlike integer addition, floating-point addition requires alignment before operating on the significands, making it a more complex multi-step process.

MIPS - Language of the Computer Building a Datapath