Compiler Design

Target Code Generator Design


Target Code Generator Design

Target code generation is the final compiler phase. It translates the intermediate representation into the target machine's instruction set. Output can be absolute machine code, relocatable machine code, or assembly language.

  • Input to Code Generator: Must ensure correctness and exact form of the IR.
  • Memory Management: Mapping names to specific runtime addresses and managing stack frames.
  • Instruction Selection: Choosing the most efficient machine instructions.
  • Register Allocation: Making optimal use of limited fast registers.
  • Evaluation Order: The order of operations heavily affects register requirements.
  • Cost Model: Accurately measuring the performance cost of instruction sequences to guide optimization choices.

A basic code generator processes three-address statements and maintains two important descriptors:

  • Register Descriptor: Tracks what variable is currently held in each register.
  • Address Descriptor: Tracks where (in a register or in memory) the current value of each variable is.

The getReg() Function

For an instruction x = y op z, the generator decides which registers to use:

  • If y is already in a register, use it; else load y.
  • If z is already in a register, use it; else load z.
  • If x has a register allocated, use it; else find a free register or spill one to memory.